Advances in semiconductor device usages have demanded ever-increasing high functional density with continuous size scaling for memory devices. This scaling process has led to the consideration of various architectures and materials in memory arrays.
The introduction of new materials to the memory device, e.g., in the formation of the memory elements and their support components, can require evaluations of different materials and compositions, together with imposing significant changes to the device fabrication process, including device structure designs to reduce leakage, thermal processing to achieve thermal stability and phase stability, and device integration process to achieve memory array performance, together with endurance, variability, and reliability.
The manufacture of novel memory architectures and materials entails the integration and sequencing of many unit processing steps, with potential new process developments, since in general, new materials are much more sensitive to process conditions than existing materials. For example, the precise sequencing and integration of the unit processing steps can enable the formation of functional devices meeting desired performance metrics such as power efficiency, signal propagation, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
High productivity combinatorial (HPC) processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). However, HPC processing techniques have not been successfully adapted to the development of current selector for non volatile memory devices in cross point memory arrays.
Therefore, there is a need to apply high productivity combinatorial techniques to the development and investigation of materials and fabrication processes for the manufacture of current selectors in non volatile memory arrays.